Back to N3 Kanji
ๅ›ž
JLPT N3 SL2 6 strokes Frequency: #50

Meanings

-times, Round, Game, Revolve, Counter For Occurrences

Radicals

ๅ›—

Decomposition

โฟดๅ›—ๅฃ

Etymology

Ideographic: Originally, a spiral signifying return

Writing Practice

Stroke 0 / 6

Stroke Order

1 vertical bottom-right-to-top-left
2 corner bottom-right-to-top-left
3 vertical bottom-right-to-top-left
4 corner bottom-right-to-top-left
5 horizontal bottom-right-to-top-left
6 horizontal bottom-to-top
On'yomi (Chinese reading)
ใ‚จ e
ใ‚ซใ‚ค kai
Kun'yomi (Japanese reading)
ใ‹ ka
ใพใ‚ mawa
ใ‚‚ใจใŠ motoo

Words Using This Kanji

737 words total
Other (20 words)
ๅ‡บๅ›ž็ทš ใ—ใ‚…ใคใ‹ใ„ใ›ใ‚“

output line

ๅ‡บ็พๅ›žๆ•ฐ ใ—ใ‚…ใคใ’ใ‚“ใ‹ใ„ใ™ใ†

number of occurrences

้›†็ฉๅ›ž่ทฏ่จ˜ๆ†ถ่ฃ…็ฝฎ ใ—ใ‚…ใ†ใ›ใใ‹ใ„ใ‚ใใŠใใใ†ใก

integrated circuit memory

ๅทกๅ›žๅ†—้•ทๆคœๆŸป ใ˜ใ‚…ใ‚“ใ‹ใ„ใ˜ใ‚‡ใ†ใกใ‚‡ใ†ใ‘ใ‚“ใ•

cyclic redundancy check

้ †ๅบๅ›ž่ทฏ ใ˜ใ‚…ใ‚“ใ˜ใ‚‡ใ‹ใ„ใ‚

sequential circuit

้›†็ฉๅ›ž่ทฏใƒกใƒขใƒช ใ—ใ‚…ใ†ใ›ใใ‹ใ„ใ‚ใƒกใƒขใƒช

integrated circuit memory

ๅทกๅ›žใ‚ปใƒผใƒซใ‚นใƒžใƒณใฎๅ•้กŒ ใ˜ใ‚…ใ‚“ใ‹ใ„ใ‚ปใƒผใƒซใ‚นใƒžใƒณใฎใ‚‚ใ‚“ใ ใ„

travelling salesman problem

้‡ๅ›žๅธฐ ใ˜ใ‚…ใ†ใ‹ใ„ใ

multiple regression

ๅทกๅ›žใƒใƒผใƒชใƒณใ‚ฐ ใ˜ใ‚…ใ‚“ใ‹ใ„ใƒใƒผใƒชใƒณใ‚ฐ

wraparound polling

้šœๅฎณๅ›žๅพฉ ใ—ใ‚‡ใ†ใŒใ„ใ‹ใ„ใตใ

fault recovery

ๅŒๅฎ‰ๅฎšใƒˆใƒชใ‚ฌใƒผๅ›ž่ทฏ ใใ†ใ‚ใ‚“ใฆใ„ใƒˆใƒชใ‚ฌใƒผใ‹ใ„ใ‚

bistable trigger circuit

ๅ‰้€ฒๅ›žๅพฉ ใœใ‚“ใ—ใ‚“ใ‹ใ„ใตใ

forward recovery

็ต„ใฟๅˆใ‚ใ›ๅ›ž่ทฏ ใใฟใ‚ใ‚ใ›ใ‹ใ„ใ‚

combinational circuit

ๅŒๅฎ‰ๅฎšๅ›ž่ทฏ ใใ†ใ‚ใ‚“ใฆใ„ใ‹ใ„ใ‚

bistable (trigger) circuit

ๅŒๅฎ‰ๅฎšใƒˆใƒชใ‚ฌๅ›ž่ทฏ ใใ†ใ‚ใ‚“ใฆใ„ใƒˆใƒชใ‚ฌใ‹ใ„ใ‚

bistable trigger circuit

ๅคš้ …ๅ›žๅธฐ ใŸใ“ใ†ใ‹ใ„ใ

polynomial regression

ๅ˜ๅฎ‰ๅฎšใƒˆใƒชใ‚ฌๅ›ž่ทฏ ใŸใ‚“ใ‚ใ‚“ใฆใ„ใƒˆใƒชใ‚ฌใ‹ใ„ใ‚

monostable trigger circuit

ๅ˜็ทšๅผๅ›ž็ทš ใŸใ‚“ใ›ใ‚“ใ—ใใ‹ใ„ใ›ใ‚“

single-wire line

ๅ˜ๅฎ‰ๅฎšๅ›ž่ทฏ ใŸใ‚“ใ‚ใ‚“ใฆใ„ใ‹ใ„ใ‚

monostable (trigger) circuit

้…ๅปถๅ›ž่ทฏ ใกใˆใ‚“ใ‹ใ„ใ‚

delay circuit